Senior Signal Integrity Engineer

1671

About the Role

We are seeking a Senior Signal Integrity Engineer to develop, validate, and optimize high-speed signaling solutions across blade- and rack-level architectures for advanced compute platforms. This role sits at the intersection of silicon, package, interconnect, board, and system design , with a strong emphasis on hands-on measurement, simulation correlation, and cross-functional technical communication.

Key Responsibilities

• End-to-end signal integrity analysis for blade- and rack-level system architectures.

• Analyze and optimize high-speed and low-speed I/O interfaces, including PCIe Gen4/5/6, Ethernet, DDR, SerDes, SPI , I2C, etc . and related interconnects.

• Perform time-domain and frequency-domain simulations using tools such as Ansys HFSS, Keysight ADS, Cadence Sigrity, CST, SPICE , or similar.

• Support hands-on lab validation using VNA, TDR, BERT, and high-speed oscilloscopes .

• Correlate simulation results with lab measurements to identify margin gaps, debug issues, and improve design methodology.

• Collaborate with silicon, package, board, connector, cable, and system design teams to optimize I/O channel performance.

• Work with interconnect vendors and ODMs to guide board layout, stack-ups, routing rules, and system design decisions.

• Review schematics, layouts, simulation results, and validation data for blade, backplane, and rack-level hardware.

• Prepare and communicate clear validation reports, measurement summaries, debug findings, and technical recommendations to internal teams, vendors, and senior technical stakeholders.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering,

Department: HW Platform Dev