Primary record

Interconnect and Compute Architect

Tenstorrent Indexed employerSanta Clara, California, United States
Source-hosted applyChecked 5h agoOther
Apply at Tenstorrent

Tenstorrent receives this application through Greenhouse. Babu Careers does not claim delivery.

Workplace

remote

Employment

Other

Published

Aug 11, 2026

Closes

No date supplied

The role

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Tenstorrent is seeking an Interconnect and Compute Architect to help define and build next-generation CPU networking architecture for both datacenter and emerging robotics/automotive applications. You will contribute to our current datacenter networking efforts while also helping to seed and specify future medium- to low-power robotics/automotive devices for AI/ML compute and sensor ingest. The initial focus will be datacenter networking, with robotics as the first target within the automotive/robotics space.

This role is remote, based out of North America.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You thrive while navigating multiple priorities and ambiguous, evolving requirements.

• You have knowledge of Ethernet network architecture and how performance is modeled.

• You have experience with die-to-die interfaces and understand associated protocols and design tradeoffs.

• You understand Ethernet networking concepts and how they map onto on-chip and off-chip fabrics

Requirements

Department: Architecture