Primary record

CPU Architect, Load-Store

Tenstorrent Indexed employerSanta Clara, California, United States
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Workplace

remote

Employment

Other

Published

Aug 11, 2026

Closes

No date supplied

The role

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

We are seeking a highly motivated and passionate CPU Architect to join our processor architecture team, focusing on the CPU’s load-store unit. In this role, you will contribute to the design, analysis, and optimization of cutting-edge CPU architectures with an emphasis on a high-performance load-store unit. This is an excellent opportunity to work alongside world class architects in high-performance computing and processor design.

This role is Remote, based out of The United States.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Responsibilities:

• Drive the architecture, micro-architecture, design and optimization of the CPU load-store unit for Tenstorrent’s high-performance out-of-order RISCV CPUs

• Propose new implementations to optimize load-store PPA

• Perform simulations, modeling, and performance analysis of advanced CPU features and state-of-the-art data prefetchers

• Collaborate with hardware and software teams to optimize memory access patterns and system performance.

• Stay up to date with industry tre

Requirements

Department: Architecture: Performance Model